Title: Exploiting hardware matrix accelerations in computer algebra

Topics: high performance computing, fast arithmetic, hardware acceleration

Address

Research team: MAX, Algebraic modeling and symbolic computation

Contacts

Context

The MAX team is searching for PhD candidates on the themes of the “ODELIX” ERC Advanced Grant. The present M2 internship proposal allows applicants to familiarize themselves with these themes. Upon successful completion of the internship, there will be an opportunity to pursue with a PhD.

Applying

Applications can be sent by email to the above contact persons; they should include a CV, a transcript of records, a letter of motivation, and optional recommendation letters. Note that we have no hard deadlines; new applications will be considered at any time of the year, as long as the Odelix project runs.

Driven by needs from artificial intelligence, modern hardware increasingly include accelerators for matrix multiplication: Intel's AMX extensions [2], Apple's undocumented matrix extensions [1, 3, 10], tensor cores on various GPUs [9], etc.

The specifics of such hardware accelerators vary heavily when it comes to the supported data types (from 8-bit to 64-bit integer and/or floating point types) and the precise kind of operations that are supported (e.g. 8 bit unsigned integer matrix multiply, accumulated into a 32 unsigned integer bit result).

The main question for this internship is whether these new accelerators can also be beneficial for other applications besides AI. For instance, can they be used to develop faster algorithms for polynomial multiplication, multiple precision arithmetic, finite field arithmetic, etc.? More generally, we are motivated by applications to computer algebra [5] and reliable computing.

A first objective will be the design of an interface for matrix accelerators on various types of hardware and to better understand the performance of such accelerators.

We next pursue with the first application for which such accelerators should be beneficial: integer matrix multiplication via Chinese remaindering [4, 8]. We will investigate for which precisions and matrix sizes the hardware accelerations become beneficial.

As a function of the available time, we will next investigate a wider range of hardware and/or other applications such as polynomial multiplication and large integer multiplication [6, 7].

We seek for excellent candidates with a background in computer science. Applicants will be required to have knowledge in algorithms, parallelism, high performance computing and complexity. Programming skills will be useful to achieve efficient implementations.